START header gEDA's netlist format Created specifically for testing of gnetlist END header START components axis.1 device=axis comp.0 device=comp conv-s32-float.0 device=conv-s32-float axis.0 device=axis hal-parport.1 device=hal-parport:out hal-parport.0 device=hal-parport:in stepgen.2 device=stepgen-type0 stepgen.1 device=stepgen-type0 sum2.0 device=sum2 stepgen.0 device=stepgen-type0 not.0 device=not and2.2 device=and2 edge.0 device=edge and2.1 device=and2 mult2.0 device=mult2 and2.0 device=and2 axis.2 device=axis mux2bit.0 device=mux2bit mux2.0 device=mux2 END components START renamed-nets END renamed-nets START nets zValid : axis.2 .home-sw-in, hal-parport.0 .pin-10-in-not zNegLim : axis.2 .pos-lim-sw-in, hal-parport.0 .pin-09-in-not zPosLim : axis.2 .pos-hard-lim, hal-parport.0 .pin-08-in-not yValid : axis.1 .home-sw-in, hal-parport.0 .pin-07-in-not yNegLim : axis.1 .pos-lim-sw-in, hal-parport.0 .pin-06-in-not yPosLim : axis.1 .pos-hard-lim, hal-parport.0 .pin-05-in-not xValid : axis.0 .home-sw-in, hal-parport.0 .pin-04-in-not xNegLim : axis.0 .pos-lim-sw-in, hal-parport.0 .pin-03-in-not xPosLim : axis.0 .pos-hard-lim, hal-parport.0 .pin-02-in-not float4 : and2.2 .in1 float3 : and2.2 .in0 float2 : and2.1 .in1 float1 : and2.1 .in0 TRUE : mux2bit.0 .in1 notlogic : mux2bit.0 .in0, not.0 .out, mux2.0 .sel somelogic : not.0 .in, mux2bit.0 .sel, mult2.0 .sel sum2 : and2.2 .out, mux2.0 .in1, mult2.0 .in1, and2.0 .in1 sum1 : mux2.0 .in0, mult2.0 .in0, and2.1 .out, and2.0 .in0 zEnable : axis.2 .amp-enable-out, hal-parport.1 .pin-14-out yEnable : axis.1 .amp-enable-out, hal-parport.1 .pin-09-out xEnable : axis.0 .amp-enable-out, hal-parport.1 .pin-08-out zDir : stepgen.2 .dir, hal-parport.1 .pin-07-out zStep : stepgen.2 .step, hal-parport.1 .pin-06-out yDir : stepgen.1 .dir, hal-parport.1 .pin-05-out yStep : stepgen.1 .step, hal-parport.1 .pin-04-out xDir : stepgen.0 .dir, hal-parport.1 .pin-03-out xStep : stepgen.0 .step, hal-parport.1 .pin-02-out END nets