![[Home]](/chips.gif)
History of JTAG Boundary Scan Example For A Mesanet 7i43
Get to know your hardware - how to do a JTAG boundary scan for a Mesanet 7i43 under Linux Ubuntu 10.10 AMD64 |
Get to know your hardware - How to do a JTAG boundary scan for a Mesanet 7i43 under Linux Ubuntu 10.10 AMD64 |
|
In this short howto I'd like to show you how to establish communication with your Mesanet 7i43 |
|
In this short how-to I'd like to show you how to establish communication with your Mesanet 7i43 |
|
Many of todays IC come with a special bus called JTAG, which is useful for debugging, programming the IC and development in general. If you have not yet come across JTAG, then please do read the wikipedia article first. |
|
Many of todays ICs come with a special bus called JTAG, which is useful for debugging, programming the IC, and development in general. If you have not yet come across [JTAG], then please do read the Wikipedia article first. |
|
Last summer, I accidentally killed the cpld on the 7i43, which is a XC9572XL. I replaced the cpld on the pcb with a new one. But unlike fpgas, cplds have to be programmed. |
|
Last summer, I accidentally killed the [CPLD] on the 7i43, which is an XC9572XL. I replaced the CPLD on the PCB with a new one. But unlike an [FPGA], CPLDs have to be programmed. |
|
# A parallel port JTAG adapter. I got mine for another fpga project at ebay.de for EUR 13,- incl. shipping. (datasheet: http://www.anvilex.de/Extern/Datasheets/DS_P009_08.pdf). There are many other JTAG adapters available, parallel port clones of the Xilinx cables and USB ones, YMMV. # And fpga board with a populated jtag header. I had to solder on a header to the 7i43 and create a small adapter cable from my cheap parallel port jtag adapter to match the pinout on the 7i43 board. # Xilinx ISE WebPACK?, which contains a program called impact. The download is huge and might take a while. The ISE webpack is free as in free beer. |
|
# A parallel port JTAG adapter. I got mine for another FPGA project at ebay.de for EUR 13,- incl. shipping. [datasheet]. There are many other JTAG adapters available, parallel port clones of the Xilinx cables and USB ones, YMMV. # An FPGA board with a populated JTAG header. I had to solder on a header to the 7i43 and create a small adapter cable from my cheap parallel port JTAG adapter to match the pinout on the 7i43 board. # Xilinx ISE WebPACK, which contains a program called impact. The download is huge and might take a while. The ISE WebPACK is free as in free beer. |
|
Then install ISE webpack. |
|
Then install ISE WebPACK. |
|
Compile the usb-driver by running make in its directory. You quite certainly might want to install compile dependancies first, see the included README. |
|
Compile the usb-driver by running make in its directory. You will certainly want to install compile dependencies first, see the included README. |
|
And please to substitute your own path. Example: |
|
And please remember to substitute your own path. Example: |
|
Now you need to set the environment variables for ISE, mine are in /home/mx/Xilinx?/12.3/ISE_DS/settings64.sh, so the command is: source /home/mx/Xilinx?/12.3/ISE_DS/settings64.sh |
|
Now you need to set the environment variables for ISE, mine are in /home/mx/Xilinx/12.3/ISE_DS/settings64.sh, so the command is: source /home/mx/Xilinx/12.3/ISE_DS/settings64.sh |
|
Then start impact in your shell by simple entering: |
|
Then start impact in your shell by simply entering: |
|
So speed up the invocation of all this I created a small shell script: impact.bash |
|
To speed up the invocation of all this I created a small shell script: impact.bash |
|
If you want to program the cpld, then look at the files I43CPLD2.JED (200k version) or I43CPLD4.JED (400k version) in the 7i43.zip file on the mesanet web page. |
|
If you want to program the CPLD, then look at the files I43CPLD2.JED (200k version) or I43CPLD4.JED (400k version) in the 7i43.zip file on the [Mesa Electronics] web page. |
|
The mesanet 7i43 fpga board |
|
The Mesa Electronics 7i43 FPGA board |
|
A parallel port jtag cable with an adapter to match the fpga board's jtag connector |
|
A parallel port JTAG cable with an adapter to match the FPGA board's JTAG connector |
|
Select Ok here |
|
Select OK here |
|
If you want to program the cpld or upload a configuration to the fpga, then select yes here, otherwise no |
|
If you want to program the CPLD or upload a configuration to the FPGA, then select yes here, otherwise no |
|
Choose a file to program the cpld |
|
Choose a file to program the CPLD |
|
|