[Home]History of Shift Register Port Expander

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Revision 10 . . February 6, 2013 6:45 pm by Pilotkip
Revision 9 . . January 28, 2013 8:44 pm by Pilotkip [Added HAL Scope screen shot.]
Revision 8 . . January 28, 2013 7:24 pm by Pilotkip [fixed reference to incorrect thread.]
Revision 7 . . January 28, 2013 3:00 pm by Pilotkip [Added component timing diagram]
Revision 6 . . January 28, 2013 2:58 pm by Pilotkip [Added schematic representation of component.]
Revision 5 . . January 28, 2013 2:05 pm by Pilotkip
Revision 4 . . (edit) January 28, 2013 2:04 pm by Pilotkip
Revision 3 . . January 28, 2013 1:59 pm by Pilotkip [Added circuit and .comp file]
Revision 2 . . January 28, 2013 1:57 pm by Pilotkip
Revision 1 . . January 28, 2013 1:44 pm by Pilotkip [Initial Entry]
  
Difference (from prior major revision) (no other diffs)

Changed: 14c14,15
used 74LS595 chips as our SIPO shift registers and 74LS597 chips for PISO.
used 74LS595 chips as our SIPO shift registers and 74LS597 chips for PISO. LS series chips are obsoltete.
We recommend using a current set of chips, such as the 74HCT595 and 74HCT597 or equivalent.

Changed: 20c21,29
inverting the RCLK signal.
inverting the RCLK signal with an inverter, like the 7404.

Pin names on the chips may be different than as shown. On a current datasheet I see the following names:
STCP = Storage Register Clock, I referred to as 'Latch', formerly 'RCLK'
SHCP = Shift register clock, formerly 'SRClock'
DS = Serial data Input, formerly 'Ser'
PL = Parallel Load, formerly 'SRLoad'

Other pins such as Output Enable and Reset should be tied high or low as appropriate.
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